The Peripheral Component Interconnect bus, which is a bus designed by Intel Corporation is a high-speed interface between the central processing unit (CPU) and peripheral devices in a computer system. The bus operates in synchronization with the clock speed of the CPU at 33 Mhz. A customized bus system for a typical high bandwidth server application is a Compact Peripheral Component Interconnect (CPCI) bus.
The CPCI bus is limited to the components that require infrequent access and are subjected to small amount of data transfers, and is therefore not suitable for communication between high-speed integrated circuits.
Conventionally, the Inter Integrated Circuit (I2C) protocol is used for establishing communication among the devices at the integrated circuit level. The I2C bus permits integrated circuits to communicate directly with each other through a bi-directional bus. The device to be connected to the bus is coupled to the serial data (SDA) wire and the serial clock (SCL) wire. The SDA wire is used for the communication of data and the SCL wire is used for control and synchronization of communication of data between the devices. The output of each electronic device is configured as an open-collector/open-drain device, wherein one or more pull-up resistors maintain a logic high value on the bus while the bus is in an inactive state.
The I2C system comprises a plurality of electronic devices connected in parallel to each other and are connected to the SCL and SDA line. If an electronic device requires data from a bus, the electronic device pulls the bus to a logic low value, through the open collector or open drain device that is placed in a conductive state to a ground potential.
U.S. Patent Publication No. 2005/0091438 A1 relates to a system and method that provides an Intelligent Platform Management Interface (IPMI) controller to control various Inter Integrated Circuit (I2C) slave devices having I2C slave drivers without any modification of the I2C slave drivers on the I2C slave devices. The I2C slave devices can be managed without an external and/or a dedicated I2C master controller.
FIG. 1 illustrates a conventional CPCI system 602 as mentioned in the aforementioned patent document, said CPCI system 602 comprising a CPCI backplane or midplane (not shown), a plurality of node cards (or blades) 606, a host node card or master card (MC) 616, a switch card (not shown), power supplies 605, fans 604, and a system control board (SCB) 603. The MC 616 includes a central processing unit (CPU) 608 to provide the on-board intelligence for the MC 616. The CPU 608 of the MC 616 is coupled to memories (not shown) containing a firmware and/or software that runs on the MC 616, IPMI controller 610, and other devices, such as a programmable logic device (PLD) 609 for interfacing an IPMI controller 610 with the CPU 608. The SCB 603 provides the control and status of the system 602, such as monitoring the healthy status of all the power supplies 605 and the fans 604 (FRUs), powering ON and OFF the FRUs, etc.
The SCB 603 is interfaced with the MC 616 via an I2C interface 611 so that the MC 616 can access and control the FRUs in the system 602. The fans 604 provide the cooling to the entire system 602. Each of the fans 604 has a fan board, which provides control, and status information about the fans and, like the SCB 603, are also controlled by the MC 616 through the I2C interface 611. The power supplies 605 provide the required power for the entire system 602. The MC 616 manages the power supplies 605 through the I2C 611 (e.g., the MC 616 determines the status of the power supplies 605 and can power the power supplies 605 ON and OFF). The node cards 606 are independent computing nodes and the MC (which may also be a node card) manages these node cards though the IPMI 612 (or IPMB).
In addition, the IPMI controller 610 has its own processing core unit and runs the IPMI protocol over the IPMB 612 to perform the management of the computing node cards 606. IPMI Controller 610 is also the central unit (or point) for the management of the system 602. The CPU 608 of the MC 616 can control the IPMI controller 610 and retrieve the system 602-status information by interfacing with the IPMI controller 610 via PLD 609. The IPMI controller 610 provides the MC 616 with the IPMB 612 (the IPMB then connects with the “intelligent FRUs,” such as node cards and switch fabric card) and the I2C 611 (the I2C interface 611 then connects with the “other FRUs,” such as fans, power supplies, and the SCB).
It can be seen from the aforementioned patent document that it is a controller that controls various slaves connected to the master. Thus, the IPMI controller cannot emulate a slave to create a multiple slave control system and adds an area overhead to the system.
Further, there is no mechanism to confirm the validity of the data written to the serial memory. The data has to be read back which is not feasible for time critical applications.
Single I2C interfaces do not have multiple slave addresses mapped to individual reusable buffers. If a single master wants to access multiple data buffers based on the command code communicated, this will increase the software overhead and communication time. Single buffer I2C peripherals increase software overhead due to software processing for each data received on the bus. Byte count and memory pointer are maintained by the software increasing the software overhead.
Thus, a need is felt for an efficient data transference system for integrated circuits that saves on area and is a speed efficient emulation system wherein emulation of the data storage is an integral part of the data accession function.